1. Field of the Invention
This invention relates to integrated circuit devices, in particular, an integrated circuit device with a power-supply voltage detection circuit to detect that a power-supply voltage goes out of predetermined regulation.
2. Description of a Related Art
Recently, there have been an increasing number of integrated “system on chip” that support embedded functions such as CPU, logic gates, memory, and so on, as well as integrated circuits with single function above.
In such an integrated circuit device, different power-supply voltages are needed for each internal circuit; thus, in order to supply each internal circuit, a plurality of regulator circuits are incorporated to generate internal power-supply voltages VDD from an external power-supply voltage EVDD.
Although the regulator circuit is configured to keep the internal power-supply voltage VDD constant by employing a feedback loop, in a case where the external power-supply voltage EVDD varies abruptly, the regulator circuit cannot respond to the variation and the internal power-supply voltage VDD varies accordingly. This causes the problems of runaways of CPU or writing failures on the memory.
In order to deal with this problem, by embedding a voltage detection circuit in the integrated circuit which detects whether the power-supply voltage goes out of regulation, a resetting procedure is usually made on CPU when the external power-supply voltage EVDD or the internal power-supply voltage VDD goes out of regulation.
FIG. 7 shows a circuit diagram of a related art that discloses the arrangement embedding a power-supply voltage detection circuit.
As shown in FIG. 7, the conventional integrated circuit device comprises a reference voltage generator circuit 1 which generates a predetermined reference voltage VREF, a regulator circuit 2 which generates the internal power-supply voltage VDD to be supplied to the internal circuit 4 from the reference voltage VREF, and a power-supply voltage detection circuit 5 which detects whether or not the internal power-supply voltage VDD from the regulator circuit 2 is out of regulation and outputs the results of the detection.
The reference voltage generator circuit 1 generates the constant reference voltage VREF by using a forward voltage of diode D1, which, for example, is described in IEEE JOURNAL OF SOLID-STATE CIRCUIT, JUNE 1977, P. 228–231.
The regulator circuit 2 comprises a differential amplifier circuit 21, a transistor 22 which supplies the internal power-supply voltage VDD to the internal circuit 4 including CPU, and four resistors Ra, Rb, Rc and Rd which divide the internal power-supply voltage VDD. The regulator circuit 2 shown in FIG. 7 is described, for example, in “Analog Electronic Circuit” Nobuo Fujii, Shoukoudou, p.162–163.
The + input terminal of the differential amplifier circuit 21 is fed with the reference voltage VREF. The − input terminal of the differential amplifier circuit 21 is fed back with the output voltage of the node between resistors Rb and Rc. In this case, the internal power-supply voltage VDD can be expressed by the following equation:VDD=((Ra+Rb+Rc+Rd)/(Rc+Rd))VREF
This means, in the regulator circuit 2 shown in FIG. 7, the internal power-supply voltage VDD can be adjusted by choosing the ratio of (Ra+Rb) to (Rc+Rd).
The power-supply voltage detection circuit 5 comprises a first comparator 51 which detects the internal power-supply voltage VDD being equal to or less than a predetermined value and a second comparator 52 which detects the internal power-supply voltage being greater than a predetermined value.
The − input terminal of the first comparator 51 is fed with the output voltage VL, where VL is the voltage at the node between resistors Ra and Rb in the regulator circuit 2. The + input terminal of the second comparator 52 is fed with the output voltage VH, where VH is the voltage at the node between resistors Rc and Rd in the regulator circuit 2. The + input terminal of the first comparator 51 and − input terminal of the second comparator 52 are fed with the reference voltage VREF.
VL and VH can be expressed by the following equation:VL=((Rb+Rc+Rd)/(Ra+Rb+Rc+Rd))VDDVH=(Rd/(Ra+Rb+Rc+Rd))VDD
If the internal power-supply voltage VDD is within regulation, both the outputs of the first comparator 51 and the second comparator 52 result in low level because of the state VREF<VL and VREF>VH.
On the other hand, if the internal power-supply voltage VDD decreases, VL and VH also decrease, and upon reaching VREF>VL, the output of the first comparator 51, OUTL, turns to high level. If the internal power-supply voltage VDD increases, VL and VH also increase, and upon reaching VREF<VH, the output of the second comparator 52, OUTH, turns to high level.
Therefore, according to the arrangement in FIG. 7, when the internal power-supply voltage VDD goes out of regulation, a detection signal indicating this voltage anomaly is generated from the first comparator 51 or the second comparator 52, and this signal prevents CPU runaway by resetting the operation of the internal circuit.
According to the conventional integrated circuit in FIG. 7, however, a sudden variation of the external power-supply voltage EVDD causes the problem that the detection signal (that is, high level) which indicates this voltage anomaly is not generated because the power-supply voltage detection circuit cannot respond to this sudden variation.
FIG. 8 and FIG. 9 show the results of simulations for VDD (the internal power-supply voltage), VREF (the reference voltage), VL (the output voltage of the node between resisters Ra and Rb), VH (the output voltage of the node between resister Rc and Rd), OUTL (the output of the first comparator), and OUTH (the output of the second comparator), where EVDD (the external power-supply voltage) is in a abrupt variation.
As shown in FIG. 8, a sudden decrease of the external power-supply voltage EVDD causes a decrease of the internal power-supply voltage VDD after the duration of response time in the regulator circuit 2. As shown in FIG. 8, for example, when the external power-supply voltage EVDD decreases from 2.7V to 1.7V, the internal power-supply voltage VDD decreases from 2.3V to 2.0V. At this time, while the first comparator 51 should have detected this voltage anomaly of the internal power-supply voltage VDD, the output OUTL remains low level. The condition VDD=2.0V can cause a runaway of CPU; thus, not being able to detect this voltage as abnormal will be a fatal defect for the products.
If the resistances of the resistors Ra, Rb, Rc and Rd are so adjusted that VL is close to the reference voltage VREF when the internal power-supply voltage VDD is in normal state, it will be possible for the first comparator 51 to result in high level when the external power-supply voltage EVDD varies in the way shown in FIG. 8. In this case, however, the detection sensitivity becomes so high that even a noise on the input of the first comparator 51 can cause the output of the first comparator 51, OUTL, to turn to high level. This results in unnecessary resets in the CPU operation.
On the other hand, as shown in FIG. 9, a sudden increase of the external power-supply voltage EVDD does not cause the variation of the internal power-supply voltage VDD, so that neither VL nor VH varies; thus, the output of the second comparator 52, OUTH, remains low level. In this case, the internal power-supply voltage VDD is in constant control so that there is no possibility of a runaway of CPU in the internal circuit 4. If, however, the external power-supply voltage EVDD exceeds the rating for each element such as reference voltage generator circuit 1 or regulator circuit 2, there is a possibility of the integrated circuit being destroyed.
For this problem, an arrangement for detecting sudden variations of the external power-supply voltage EVDD is proposed by, for example, Japanese Unexamined Patent Application Publication No. 10-288634. The arrangement of the power-supply voltage detection circuit described in this conventional art is shown in FIG. 10.
As shown in FIG. 10, a power-supply voltage detection circuit disclosed in the above conventional art comprises four resistors R1, R2, R3, and R4 which divide the external power-supply voltage EVDD, a first comparator 61 which detects a sudden decrease of the external power-supply voltage EVDD, a second comparator 62 which detects a sudden increase of the external power-supply voltage EVDD, an OR gate 63 which outputs the OR output signal of the first comparator 61 and the second comparator 62, and a set of resistor R5 and capacitor Cx which charges and discharges one of the inputs of the first comparator 61 and the second comparator 62.
The − input terminal of the first comparator 61 is fed with the output voltage of the node between resistors R1 and R2 (node A), and the + input terminal of the second comparator 62 is fed with the output voltage of the node between resistors R3 and R4 (node B). The + input terminal of the first comparator 61 and − input terminal of the comparator 62 (node C) are grounded via capacitor Cx, and are fed with the output voltage of the node between resistors R2 and R3 via resistor R5.
In the power-supply voltage detection circuit of this arrangement shown in FIG. 10, setting R3>R5 results in VA>VC>VB, where VA, VB and VC represent the output voltages for normal state at node A, B and C respectively. In this state, both the outputs of the first comparator 61 and the second comparator 62 are low level.
If the external power-supply voltage EVDD suddenly decreases from the state above, the output voltage VA at node A abruptly varies in response to the decrease, and the output voltage VC at node C decreases with the time-constant defined by the capacitor Cx and resistor R5, resulting in an inversion of the relation between VA at node A and VC at node C. This inversion allows the first comparator 61 to output high level.
Also, if the external power-supply voltage EVDD suddenly increases, the output voltage VB at node B abruptly varies in response to the increase, and the output voltage VC at node C increases with the time-constant defined by the capacitor Cx and resistor R5, resulting in an inversion of the relation between VB at node B and VC at node C. This inversion allows the second comparator 62 to output high level.
If the power-supply voltage varies gradually, the relations among output voltages VA, VB and VC at nodes A, B and C do not vary; thus, both the outputs of the first comparator 61 and the second comparator 62 remain low level.
As mentioned above, in the conventional power-supply voltage detection circuit shown in FIG. 7, there is a problem that sudden variations of the external power-supply voltage EVDD cannot be detected. Further, there will be another problem that if the detection sensitivity is raised in order to detect sudden variations of the external power-supply voltage EVDD, the detector will unnecessarily respond to noises and wrongly output detection signals indicating voltage anomalies, resulting in unnecessary resets in the CPU operation.
On the other hand, although the power-supply voltage detection circuit in FIG. 10 can detect sudden variations of the power-supply voltage, if the power-supply voltage varies gradually, voltage anomalies cannot be detected.
While, by combining the circuits of FIG. 7 and FIG. 10, it is possible to achieve the power-supply voltage detection circuit capable of detecting sudden and gradual variations of the power-supply voltage, the size of such a circuit would be larger, resulting in other problems of larger footprint and higher price of the chip.